器件名称:
MC74AC113N
功能描述:
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
文件大小:
184.82KB 共6页
简 介:
MC74AC113 MC74ACT113 Dual JK Negative EdgeTriggered FlipFlop The MC74AC113/74ACT113 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together. Asynchronous Inputs: LOW input to SD (Set) sets Q to HIGH level Set is independent of clock Outputs Source/Sink 24 mA ′ACT113 Has TTL Compatible Inputs DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP N SUFFIX CASE 646-06 PLASTIC CONNECTION DIAGRAM VCC 14 CP2 13 K2 12 J CP K K CP J 1 CP1 2 K1 3 J1 J2 11 SD2 10 Q2 9 Q Q Q SD 4 SD1 5 Q1 Q 6 Q1 7 GND 4 SD Q2 8 D SUFFIX CASE 751A-03 PLASTIC SD LOGIC SYMBOL 10 SD Q 5 11 13 Q 6 12 J CP K Q 8 Q 9 MODE SELECT — TRUTH TABLE Inputs Operating Mode SD Set Toggle Load “0” (Reset) Load “1” (Set) Hold L H H H H J X h l h l K X h h l l Q H q L H q Q L q H L q Outputs 3 1 2 J CP K VCC = PIN 14 GND = PIN 7 H, h = HIGH Voltage Level L, l = LOW Voltage Level X = Don’t Care l, h (q) = Lower case letters indicate the state of the referenced input (or output) one set-up time prior to the HIGH to LOW clock transition. FACT DATA 5-1 MC74AC113 MC74ACT113 LOGIC DIAGRAM (Each Flip-Flop) Q 5(9) Q 6(8) J 3(11) 1(13) CLOCK (CP) SET (SD) 4(10) K 2(12) MAXIMUM RATINGS* Symbol VCC Vin Vout Iin Iout ICC Tstg Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (……
