器件名称:
MC74F379D
功能描述:
QUAD PARALLEL REGISTER WITH ENABLE
文件大小:
61.63KB 共3页
简 介:
MC54/74F379 QUAD PARALLEL REGISTER The MC54/74F379 is a 4-bit register with a buffered common enable. This device is similar to the F175 but features the common Enable rather than common Master Reset. The F379 consists of four edge-triggered D-type flip-flops with individual D inputs and Q and Q outputs. The Clock (CP) and Enable (E) inputs are common to all flip-flops. When E is HIGH, the register will retain the present data independent of the CP input. The Dn and E inputs can change when the clock is in either state, provided that the recommended setup and hold times are observed. This circuit is designed to prevent false clocking by transitions on the E input. QUAD PARALLEL REGISTER WITH ENABLE FAST SCHOTTKY TTL Edge-Triggered D-Type Inputs Buffered Positive Edge-Triggered Clock Buffered Common Enable Input True and Complement Outputs CONNECTION DIAGRAM (TOP VIEW) VCC 16 Q3 15 Q3 14 D3 13 D2 12 Q2 11 Q2 10 CP 9 J SUFFIX CERAMIC CASE 620-09 16 1 16 1 N SUFFIX PLASTIC CASE 648-08 1 E 2 Q0 3 Q0 4 D0 5 D1 6 Q1 7 Q1 8 GND 16 1 D SUFFIX SOIC CASE 751B-03 FUNCTION TABLE Inputs E H L L H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care NC = No Change ORDERING INFORMATION Outputs Dn X H L Qn NC H L Qn NC L H 13 12 5 4 1 MC54FXXXJ MC74FXXXN MC74FXXXD Ceramic Plastic SOIC CP LOGIC SYMBOL Q3 Q2 Q1 Q0 15 14 10 11 7 6 2 3 D3 D2 D1 D0 E 9 VCC = PIN 16 GND = PIN 8 FAST AND LS TTL DATA 4-176 MC54/74F379 LOGIC DIAGRAM D0 CP CP E Q E Q0 Q0 Q1 Q1 Q2 Q2 ……
