器件名称:
MC74VHC125
功能描述:
Quad Bus Buffer
文件大小:
164.71KB 共8页
简 介:
MC74VHC125 Quad Bus Buffer with 3–State Control Inputs The MC74VHC125 is a high speed CMOS quad bus buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The MC74VHC125 requires the 3–state control input (OE) to be set High to place the output into the high impedance state. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7V, allowing the interface of 5V systems to 3V systems. http://onsemi.com High Speed: tPD = 3.8ns (Typ) at VCC = 5V Low Power Dissipation: ICC = 4A (Max) at TA = 25°C High Noise Immunity: VNIH = VNIL = 28% VCC Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2V to 5.5V Operating Range Low Noise: VOLP = 0.8V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300mA ESD Performance: HBM > 2000V; Machine Model > 200V Chip Complexity: 72 FETs or 18 Equivalent Gates LOGIC DIAGRAM Active–Low Output Enables A1 OE1 A2 OE2 A3 OE3 A4 OE4 2 1 5 4 9 10 12 13 11 8 Y3 6 3 Y1 14–LEAD SOIC D SUFFIX CASE 751A 14–LEAD TSSOP DT SUFFIX CASE 948G 14–LEAD SOIC EIAJ M SUFFIX CASE 965 PIN CONNECTION AND MARKING DIAGRAM (Top View) OE1 A1 Y1 OE2 A2 Y2 GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC OE4 A4 Y4 OE3 A3 Y3 Y2 For detailed package marking information,……
