器件名称:
PACE1757M
功能描述:
COMPLETE EMBEDDED CPU SUBSYSTEM
文件大小:
651.24KB 共34页
简 介:
PACE1757M/ME COMPLETE EMBEDDED CPU SUBSYSTEM FEATURES Implements complete MIL-STD-1750A ISA including optional MMU, MFSR, and BPU functions. Two throughput options: P1757M 2.5MIPS USAF Dais Mix (Inc.Flt.Pt.)@40 MHz P1757ME 3.6MIPS USAF Dais Mix (Inc.Flt.Pt.)@40 MHz Programmable memory and I/O data wait state generation permits up to four different memory speeds in the same system. Programmable address wait states. Sixteen levels of interrupts are provided per MIL-STD-1750A. Interrupts can be either edge- or level-sensitive. Fault detection and handling Programmable detection of unimplemented memory or illegal I/O addresses. Full implementation of MIL-STD-1750A fault register. External address error detection. Testability and diagnostics. First falling address and data registers. Built in test - runs automatically at power on and after each reset. All hardware blocks and external busses examined. Hardware pass/fail for catastrophic failures. Status register indicates failed test. Console operating mode which allows operator to examine and change contents of registers within the CPU, any system memory location, or the I/O subsystems. Single 144-pin Quad straight lead or Gullwing 1.5 square inches of board surface. Operating temperature range -55 to +125°C; single 5V ± 10% VCC power supply; power dissipation < 1.9W (worst case at 40 MHz). All MIL-STD-1750A data formats and address types implemented. P1757ME includes additional matrix and vector instructions to enhance throughp……
