器件名称:
TC59LM913AMG-50
功能描述:
MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
文件大小:
500.63KB 共46页
简 介:
TC59LM913AMG-50 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC 512Mbits Network FCRAM1 (SSTL_2 Interface) 4,194,304-WORDS × 8 BANKS × 16-BITS DESCRIPTION Lead-Free Network FCRAMTM is Double Data Rate Fast Cycle Random Access Memory. TC59LM913AMG is Network FCRAMTM containing 536,870,912 memory cells. TC59LM913AMG is organized as 4,194,304-words × 8 banks × 16 bits. TC59LM913AMG feature a fully synchronous operation referenced to clock edge whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexistence. TC59LM913AMG can operate fast core cycle compared with regular DDR SDRAM. TC59LM913AMG is suitable for Network, Server and other applications where large memory density and low power consumption are required. The Output Driver for Network FCRAMTM is capable of high quality fast data transfer under light loading condition. FEATURES PARAMETER tCK tRC tRAC Clock Cycle Time (min) Random Access Time (max) CL = 4 TC59LM913AMG-50 5.0 ns 25.0 ns 22.0 ns 240 mA 80 mA 20 mA Random Read/Write Cycle Time (min) IDD1S Operating Current (single bank) (max) lDD2P Power Down Current (max) lDD6 Self-Refresh Current (max) Fully Synchronous Operation Double Data Rate (DDR) Data input/output are synchronized with both edges of DQS. Differential Clock (CLK and CLK ) inputs CS , FN and all address input signals are sampled on the positive edge of CLK. Output data (DQs and DQS) is aligne……
