器件名称:
SM320C6201B_06
功能描述:
DIGITAL SIGNAL PROCESSOR
文件大小:
932.52KB 共64页
简 介:
SM320C6201B, SMJ320C6201B DIGITAL SIGNAL PROCESSOR SGUS031B – APRIL 2000 – REVISED AUGUST 2001 D Highest Performance Fixed-Point Digital Signal Processor (DSP) SM/SMJ320C6201B – 5-, 6.7-ns Instruction Cycle Time – 150 and 200-MHz Clock Rate – Eight 32-Bit Instructions/Cycle – 1200 and 1600 MIPS VelociTI Advanced Very Long Instruction Word (VLIW) C62x CPU Core – Eight Independent Functional Units: – Six ALUs (32-/40-Bit) – Two 16-Bit Multipliers (32-Bit Results) – Load-Store Architecture With 32 32-Bit General-Purpose Registers – Instruction Packing Reduces Code Size – All Instructions Conditional Instruction Set Features – Byte-Addressable (8-, 16-, 32-Bit Data) – 32-Bit Address Range – 8-Bit Overflow Protection – Saturation – Bit-Field Extract, Set, Clear – Bit-Counting – Normalization 1M-Bit On-Chip SRAM – 512K-Bit Internal Program/Cache (16K 32-Bit Instructions) – 512K-Bit Dual-Access Internal Data (64K Bytes) Organized as Two Blocks for Improved Concurrency 32-Bit External Memory Interface (EMIF) – Glueless Interface to Synchronous Memories: SDRAM and SBSRAM – Glueless Interface to Asynchronous Memories: SRAM and EPROM Four-Channel Bootloading Direct-Memory-Access (DMA) Controller with an Auxiliary Channel 16-Bit Host-Port Interface (HPI) – Access to Entire Memory Map AA Y W V U T R P N M L K J H G F E D C B A GLP 429-PIN BALL GRID ARRAY (BGA) PACKAGE (BOTTOM VIEW) D D 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 D Two Multichannel Buffered Serial……
