器件名称:
SPI-4
功能描述:
Core w/ FIFOs V1.0 For Altera PLDs
文件大小:
106.32KB 共3页
简 介:
odel are Standards to Silicon Product Brief SPI-4 Phase 1 Core w/ FIFOs V1.0 For Altera PLDs June 2001 Benefits Faster FPGA and ASIC development for improved time-to-market with FlexBUS4 functions Lower development cost through design reuse Available source code licensing for easy design integration and migration to gate arrays or ASICs Ample design flexibility using control signals and generics/parameters Verified functionality and standards compliance Features OIF-compliant SPI-4 Phase 1 (compatible with AMCC FlexBUS-4) with FIFOs ATM, Packet Over SONET (POS), and Direct Data Mapping1 modes Single- and multi-link operation, scalable from 1 to 16 links. Programmable per-port bandwidth allocation Programmable FIFO size with programmable almost empty/almost full thresholds. Programmable burst size Automatic link selection in the Source block based on Source FIFO threshold and flow control information. 64-bit data bus width. Parity generation/checking data and control words over Description The Optical Interworking Forum’s (OIF) SPI4 Phase 1 interface allows the interconnection of Physical Layer devices to Link Layer devices in 10Gb/s ATM, POS, and Ethernet applications. Modelware’s SPI-4 Phase 1 core performs the interface functions on both sides of the interface as shown in Figure 1and Figure 2. Spi4 Altera’s Atlantic Interface on user’s side. Full synchronous design, exceeds: Clk = 200 MHz Fully automatic test bench including driver/monitor. Easy……
