器件名称:
MC74HC73ADG
功能描述:
Dual J-K Flip-Flop with Reset HighPerformance SiliconGate CMOS
文件大小:
160.88KB 共9页
简 介:
MC74HC73A Dual J-K Flip-Flop with Reset HighPerformance SiliconGate CMOS The MC74HC73A is identical in pinout to the LS73. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Each flipflop is negativeedge clocked and has an activelow asynchronous reset. The MC74HC73A is identical in function to the HC107, but has a different pinout. Features 14 1 http://onsemi.com MARKING DIAGRAMS 14 PDIP14 N SUFFIX CASE 646 1 14 14 1 SOIC14 D SUFFIX CASE 751A 1 14 14 1 TSSOP14 DT SUFFIX CASE 948G 1 HC 73A ALYWG G HC73AG AWLYWW MC74HC73AN AWLYYWWG Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 mA High Noise Immunity Characteristic of CMOS Devices In Compliance with the JEDEC Standard No. 7.0 A Requirements Chip Complexity: 92 FETs or 23 Equivalent Gates These are PbFree Devices LOGIC DIAGRAM J1 CLOCK 1 K1 RESET 1 J2 CLOCK 2 K2 RESET 2 14 1 3 2 7 5 10 6 PIN 4 = VCC PIN 11 = GND 8 Q2 13 Q1 12 Q1 PIN ASSIGNMENT CLOCK 1 RESET 1 K1 VCC CLOCK 2 9 RESET 2 Q2 J2 1 2 3 4 5 6 7 14 13 12 11 10 9 8 J1 Q1 Q1 GND K2 Q2 Q2 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = PbFree Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. FUNCTION TABLE Inputs Reset L H……
