器件名称:
74HC125
功能描述:
Quad 3State Noninverting Buffers
文件大小:
132.61KB 共8页
简 介:
74HC125 Quad 3State Noninverting Buffers HighPerformance SiliconGate CMOS The 74HC125 is identical in pinout to the LS125. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC125 noninverting buffer is designed to be used with 3state memory address drivers, clock drivers, and other busoriented systems. The device has four separate output enables that are activelow. Features 14 1 http://onsemi.com MARKING DIAGRAMS 14 SOIC14 D SUFFIX CASE 751A 1 HC125G AWLYWW Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 mA High Noise Immunity Characteristic of CMOS Devices In Compliance with the JEDEC Standard No. 7A Requirements ESD Performance: HBM > 2000 V; Machine Model > 200 V Chip Complexity: 72 FETs or 18 Equivalent Gates These are PbFree Devices 14 14 1 TSSOP14 DT SUFFIX CASE 948G 1 HC 125 ALYWG G A = Assembly Location L, WL = Wafer Lot Y = Year W, WW = Work Week G or G = PbFree Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. Semiconductor Components Industries, LLC, 2007 March, 2007 Rev. 0 1 Publication Order Number: 74HC125/D 74HC125 PIN ASSIGNMENT OE1 A1 Y1 OE2 A2 Y2 GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC OE4 A4 Y4 OE3 A3 Y3 OE1 A2 OE2 A3 1 5 4 9……
