器件名称:
A500K050-FG208PP
功能描述:
ProASIC 500K Family
文件大小:
3176.69KB 共72页
简 介:
Discontinued – v3.0 ProASIC 500K Family F ea t u re s an d B e n e fi t s H ig h C a p ac it y I/O 100,000 to 475,000 System Gates 14k to 63k Bits of Two-Port SRAM 106 to 440 User I/Os P e r f o r m an c e Mixed 2.5V/3.3V Support with Individually-Selectable Voltage and Slew Rate 3.3V, PCI Compliance (PCI Revision 2.2) S e c ur e P r o gr a m m in g The Industry’s Most Effective Security Key Prevents Read Back of Programming Bit Stream S t a n da r d F P G A a nd A S I C D es ig n F lo w 33 MHz PCI 32-bit PCI Internal System Performance up to 250 MHz External System Performance up to 100 MHz Lo w P ow e r Low Impedance Flash Switches Segmented Hierarchical Routing Structure Small, Efficient Logic Cells H ig h P e r f o r m a nc e R o u t in g H ie r ar ch y Flexibility with Choice of Industry-Standard Front-End Tools Efficient Design Through Front-End Timing and Gate Optimization ISP Support In-System Programming (ISP) with Silicon Sculptor and Flash Pro S R A M s a nd F I F O s Ultra Fast Local Network Efficient Long Line Network High Speed Very Long Line Network High Performance Global Network Up to 150 MHz Synchronous and Asynchronous Operation Netlist Generator Ensures Optimal Usage of Embedded Memory Blocks B o u nd a r y S c an T e st No nv o la t ile a n d Re pro g r am m a bl e Fl as h T e c hn o log y IEEE Std. 1149.1 (JTAG) Compliant Live at Power Up No Configuration Device Required Retains Programmed Design During Power-Down/ Po……
