器件名称:
MC100E154FN
功能描述:
5-BIT 2:1 MUX-LATCH
文件大小:
107.22KB 共4页
简 介:
MOTOROLA SEMICONDUCTOR TECHNICAL DATA 5Bit 2:1 MuxLatch The MC10E/100E154 contains five 2:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output data is controlled by the multiplexer select control, SEL. A logic HIGH on either LEN1 or LEN2 (or both) latches the outputs. The Master Reset (MR) overrides all other controls to set the Q outputs LOW. MC10E154 MC100E154 5-BIT 2:1 MUX-LATCH 850ps Max. LEN to Output 825ps Max. D to Output Differential Outputs Asynchronous Master Reset Dual Latch-Enables Extended 100E VEE Range of – 4.2V to – 5.46V 75k Input Pulldown Resistors Pinout: 28-Lead PLCC (Top View) D4b 25 SEL LEN1 LEN2 VEE MR D0a D0b 26 27 28 1 2 3 4 5 D1a 6 D1b 7 D2a 8 9 10 Q0 11 Q0 D4a 24 D3b 23 D3a VCCO 22 21 Q4 20 Q4 19 18 17 16 15 14 13 12 Q3 Q3 FN SUFFIX PLASTIC PACKAGE CASE 776-02 LOGIC DIAGRAM VCC D0a Q2 Q2 Q1 Q1 D1a D1b MUX SEL Q D EN Q R Q D EN Q R Q D EN Q R Q1 Q1 D0b MUX SEL Q D EN Q R Q0 Q0 D2a D2b D3a MUX SEL Q2 Q2 D2b VCCO * All VCC and VCCO pins are tied together on the die. MUX SEL Q3 Q3 PIN NAMES Pin D0a – D4a D0b – D4b SEL LEN1, LEN2 MR Q0 – Q4 Q0 – Q4 Function Input Data a Input Data b Data Select Input Latch Enables Master Reset True Outputs Inverted Outputs D3b D4a D4b MUX SEL Q D EN Q R Q4 Q4 SEL LEN1 LEN2 TRUTH TABLE SEL H L 12/93 Data a b MR Motorola, Inc. 1996 2–1 REV 2 MC10E154 MC100E154 DC CHARACTERISTICS (VEE = ……
