器件名称:
MC100E156FN
功能描述:
3-BIT 4:1 MUX-LATCH
文件大小:
106.78KB 共4页
简 介:
MOTOROLA SEMICONDUCTOR TECHNICAL DATA 3Bit 4:1 MuxLatch The MC10E/100E156 contains three 4:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output date is controlled by the multiplexer select controls (SEL0, SEL1). A logic HIGH on either LEN1 or LEN2 (or both) latches the outputs. The Master Reset (MR) overrides all other controls to set the Q outputs LOW. MC10E156 MC100E156 3-BIT 4:1 MUX-LATCH 950ps Max. D to Output 850ps Max. LEN to Output Differential Outputs Asynchronous Master Reset Dual Latch-Enables Extended 100E VEE Range of – 4.2V to – 5.46V 75k Input Pulldown Resistors Pinout: 28-Lead PLCC (Top View) D1b 25 SEL0 SEL1 MR VEE LEN1 LEN2 D1c 26 27 28 1 2 3 4 5 D1d 6 D0a 7 D0b 8 D0c 9 10 11 Q0 D1a D1b D1c D1d D1a 24 D2d 23 D2c 22 D2b 21 D2a VCCO 20 19 18 17 16 15 14 13 12 Q2 Q2 VCC Q1 Q1 VCCO Q0 D0a D0b D0c D0d FN SUFFIX PLASTIC PACKAGE CASE 776-02 LOGIC DIAGRAM D EN R Q0 Q0 4:1 MUX D0d VCCO 4:1 MUX D EN R Q1 Q1 * All VCC and VCCO pins are tied together on the die. PIN NAMES Pin D0x – D3x SEL0, SEL1 LEN1, LEN2 MR Q0 – Q2 Q0 – Q2 Function Input Data Select Inputs Latch Enables Master Reset True Outputs Inverted Outputs D2a D2b D2c D2d 4:1 MUX D EN R Q2 Q2 SEL0 SEL1 LEN1 LEN2 MR FUNCTION TABLE SEL1 L L H H 7/96 SEL0 L H L H Data a b c d Motorola, Inc. 1996 2–1 REV 3 MC10E156 MC100E156 DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO ……
