器件名称:
AD9680
功能描述:
AD9680 ADC具有以往产品中没有的动态范围性能，可以将直流信号转换为2 GHz输入数字信号，从而使系统设计人员拥有更多的自由度，来权衡考量信号带宽、噪声和线性度。实施直接RF采样架构则可消除模拟下变频级及其相关噪声和成本，并且更多的前端配置和调谐可以全部在数字域完成。
文件大小:
1754.5KB 共64页
简 介:
Data Sheet FEATURES JESD204B (Subclass 1) coded serial digital outputs 1.65 W total power per channel at 1 GSPS (default settings) SFDR = 85 dBFS at 340 MHz, 80 dBFS at 1 GHz SNR = 65.3 dBFS at 340 MHz (AIN = 1.0 dBFS), 61.4 dBFS at 1 GHz ENOB = 10.8 bits at 10 MHz DNL = ±0.5 LSB INL = ±2.5 LSB Noise density = 154 dBFS/Hz at 1 GSPS 1.25 V, 2.5 V, and 3.3 V dc supply operation No missing codes Internal ADC voltage reference Flexible input range and termination impedance 1.46 V p-p to 1.94 V p-p (1.70 V p-p nominal) 400 Ω, 200 Ω, 100 Ω, and 50 Ω differential 2 GHz usable analog input full power bandwidth 95 dB channel isolation/crosstalk Amplitude detect bits for efficient AGC implementation 2 integrated wideband digital processors per channel 12-bit NCO, up to 4 cascaded half-band filters Differential clock input Integer clock divide by 1, 2, 4, or 8 Flexible JESD204B lane configurations Small signal dither 14-Bit, 1 GSPS JESD204B, Dual Analog-to-Digital Converter AD9680 FUNCTIONAL BLOCK DIAGRAM AVDD1 AVDD2 AVDD3 AVDD1_SR DVDD DRVDD SPIVDD (1.25V) (2.5V) (3.3V) (1.25V) (1.25V) (1.25V) (1.8V TO 3.3V) BUFFER DDC FAST DETECT FD_A JESD204B HIGH SPEED SERIALIZER + Tx OUTPUTS VIN+A VIN–A ADC CORE 14 4 FD_B VIN+B VIN–B 14 DDC SERDOUT0± SERDOUT1± SERDOUT2± SERDOUT3± ADC CORE BUFFER CONTROL REGISTERS V_1P0 FAST DETECT CLOCK GENERATION JESD204B SUBCLASS 1 CONTROL SYNCINB± SYSREF± CLK+ CLK– ÷2 ÷4 ÷8 SPI CONTROL AD9680 PDWN/ STBY 11752-001 AGND DRGND DGND SDIO SCLK CS……
