器件名称:
ZL50015QCC
功能描述:
Enhanced 1 K Digital Switch with Stratum 4E DPLL
文件大小:
916.46KB 共122页
简 介:
ZL50015 Enhanced 1 K Digital Switch with Stratum 4E DPLL Data Sheet Features 1024 channel x 1024 channel non-blocking digital Time Division Multiplex (TDM) switch at 4.096, 8.192 and 16.384 Mbps or using a combination of ports running at 2.048, 4.096, 8.192 and 16.384 Mbps 16 serial TDM input, 16 serial TDM output streams Integrated Digital Phase-Locked Loop (DPLL) exceeds Telcordia GR-1244-CORE Stratum 4E specifications Output clocks have less than 1 ns of jitter (except for the 1.544 MHz output) DPLL provides holdover, freerun and jitter attenuation features with four independent reference source inputs Exceptional input clock cycle to cycle variation tolerance (20 ns for all rates) VDD_CORE VDD_IO VDD_COREA VDD_IOA January 2006 Ordering Information ZL50015GAC 256 Ball PBGA ZL50015QCC 256 Lead LQFP ZL50015QCC1 256 Lead LQFP* ZL50015GAG2 256 Ball PBGA** *Pb Free Matte Tin **Pb Free Tin/SilverCopper -40°C to +85 °C Trays Trays Trays Trays Output streams can be configured as bidirectional for connection to backplanes Per-stream input and output data rate conversion selection at 2.048 Mbps, 4.096 Mbps, 8.192 Mbps or 16.384 Mbps. Input and output data rates can differ Per-stream high impedance control outputs (STOHZ) for 8 output streams VSS RESET ODE STi[15:0] FPi CKi MODE_4M0 MODE_4M1 REF0 REF1 REF2 REF3 REF_FAIL0 REF_FAIL1 REF_FAIL2 REF_FAIL3 S/P Converter Data Memory P/S Converter STio[15:0] Input Timing Connection Memory Output HiZ Control STOHZ[7……
