器件名称: 74AC11139D
功能描述: DUAL 2-LINE DECODER/DEMULTIPLEXER
文件大小: 95.83KB 共6页
简 介:74AC11139 DUAL 2-LINE DECODER/DEMULTIPLEXER
SCAS070B – JULY 1989 – REVISED APRIL 1996
D D D D D D
Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems Incorporates Two Enable Inputs to Simplify Cascading and/or Data Reception Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) 1-m Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline (D) and Thin Shrink Small-Outline (PW) Packages, and Standard Plastic 300-mil DIPs (N)
D, N, OR PW PACKAGE (TOP VIEW)
1Y1 1Y2 1Y3 GND 2Y0 2Y1 2Y2 2Y3
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
1Y0 1A 1B 1G VCC 2G 2A 2B
description
The 74AC11139 circuit is designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible. The 74AC11139 is composed of two individual 2-line to 4-line decoders in a single package. The active-low enable input can be used as a data line in demultiplexing applications. This decoder/demultiplexer features fully buffered inputs, each of wh……
