器件名称:
74HC03N
功能描述:
Quad 2-input NAND gate
文件大小:
55.97KB 共8页
简 介:
INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT03 Quad 2-input NAND gate Product specication File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specication Quad 2-input NAND gate FEATURES Level shift capability Output capability: standard (open drain) ICC category: SSI GENERAL DESCRIPTION The 74HC/HCT03 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns 74HC/HCT03 The 74HC/HCT03 provide the 2-input NAND function. The 74HC/HCT03 have open-drain N-transistor outputs, which are not clamped by a diode connected to VCC. In the OFF-state, i.e. when one input is LOW, the output may be pulled to any voltage between GND and VOmax. This allows the device to be used as a LOW-to-HIGH or HIGH-to-LOW level shifter. For digital operation and OR-tied output applications, these devices must have a pull-up resistor to establish a logic HIGH level. TYPICAL SYMBOL tPZL/ tPLZ CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD × VCC2× fi + ∑ (CL × VCC2 × fo) + ∑ (VO2/RL) × duty factor LOW, where: fi = input frequency in MHz fo = output frequency in MHz……
