器件名称:
74LV02A
功能描述:
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
文件大小:
703.01KB 共16页
简 介:
SN54LV02A, SN74LV02A QUADRUPLE 2INPUT POSITIVENOR GATES SCLS390J APRIL 1998 REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP (Output Ground Bounce) D D D Ioff Supports Partial-Power-Down Mode D D Operation Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101) SN54LV02A . . . FK PACKAGE (TOP VIEW) <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V, TA = 25°C Support Mixed-Mode Voltage Operation on All Ports 1Y VCC GND NC No internal connection description/ordering information The ’LV02A devices are quadruple 2-input positive-NOR gates designed for 2-V to 5.5-V VCC operation. The ’LV02A devices perform the Boolean function Y = A + B or Y = A B in positive logic. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. ORDERING INFORMATION TA PACKAGE QFN RGY SOIC D SOP NS 40°C to 85°C SSOP DB Reel of 1000 Tube of 50 Reel of 2500 Reel of 2000 Reel of 2000 Tube of 90 TSSOP PW TVSOP DGV CDIP J 55°C to 125°C CFP W LCCC FK Reel of 2000 Reel of 250 Reel of 2000 Tube of 25 Tube of 150 Tube of 55 ORDERABLE PART NUMBER SN74LV02ARGYR SN74LV02AD SN74LV02ADR SN74LV02ANSR SN74LV02ADBR SN74LV02APW SN74LV02APWR SN74LV02AP……
