器件名称:
74LVQ00
功能描述:
LOW VOLTAGE CMOS QUAD 2-INPUT NAND GATE
文件大小:
285.1KB 共11页
简 介:
lvq00.fm Page 1 Thursday, July 29, 2004 2:28 PM 74LVQ00 LOW VOLTAGE CMOS QUAD 2-INPUT NAND GATE s s s s s s s s s s s HIGH SPEED: tPD = 5.5ns (TYP.) at VCC = 3.3 V COMPATIBLE WITH TTL OUTPUTS LOW POWER DISSIPATION: ICC = 2A (MAX.) at TA=25°C LOW NOISE: VOLP = 0.3V (TYP.) at VCC = 3.3V 75 TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 12mA (MIN) at VCC = 3.0V PCI BUS LEVELS GUARANTEED AT 24 mA BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 3.6V (1.2V Data Retention) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 00 IMPROVED LATCH-UP IMMUNITY SOP TSSOP Table 1: Order Codes PACKAGE SOP TSSOP T&R 74LVQ00MTR 74LVQ00TTR DESCRIPTION The 74LVQ00 is a low voltage CMOS QUAD 2-INPUT NAND GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications. The internal circuit is composed of 3 stages including buffer output, which enables high noise immunity and stable output. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. Figure 1: Pin Connection And IEC Logic Symbols July 2004 Rev. 5 1/11 lvq00.fm Page 2 Thursday, July 29, 2004 2:28 PM 74LVQ00 Figure 2: Input And Output Equivalent Circuit Table 2: Pin Description PIN N° 1, 4, 9, 12 2, 5, 10, 13 3, 6, 8, 11 7 14 SYMBOL 1A to 4A 1B to 4B 1Y to 4Y GND VCC NAME AND FUNCTION D……
