器件名称:
CD54AC139F3A
功能描述:
DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS
文件大小:
204.38KB 共9页
简 介:
CD54AC139, CD74AC139 DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS SCHS332 – MARCH 2003 D D D D D D D D AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the Supply Voltage Buffered Inputs Incorporate Two Enable Inputs to Simplify Cascading and/or Data Reception Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Balanced Propagation Delays ±24-mA Output Drive Current – Fanout to 15 F Devices SCR-Latchup-Resistant CMOS Process and Circuit Design Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015 CD54AC139 . . . F PACKAGE CD74AC139 . . . E OR M PACKAGE (TOP VIEW) 1G 1A 1B 1Y0 1Y1 1Y2 1Y3 GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC 2G 2A 2B 2Y0 2Y1 2Y2 2Y3 description/ordering information The ’AC139 devices are dual 2-line to 4-line decoders/demultiplexers designed for 1.5-V to 5.5-V VCC operation. These devices are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When used with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible. The active-low enable (G) input can be used as a data line in demultiplexing applic……
