器件名称:
CD54HC75F3A
功能描述:
Dual 2-Bit Bistable Transparent Latch
文件大小:
348.92KB 共15页
简 介:
CD54HC75, CD74HC75, CD54HCT75, CD74HCT75 Data sheet acquired from Harris Semiconductor SCHS135F March 1998 - Revised October 2003 Dual 2-Bit Bistable Transparent Latch Description The ’HC75 and ’HCT75 are dual 2-bit bistable transparent latches. Each one of the 2-bit latches is controlled by separate Enable inputs (1E and 2E) which are active LOW. When the Enable input is HIGH data enters the latch and appears at the Q output. When the Enable input (1E and 2E) is LOW the output is not affected. Features True and Complementary Outputs [ /Title (CD74 HC75, CD74 HCT75 ) /Subject (Dual 2-Bit Bistabl e Buffered Inputs and Outputs Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads Wide Operating Temperature Range . . . -55oC to 125oC Balanced Propagation Delay and Transition Times Signicant Power Reduction Compared to LSTTL Logic ICs HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1A at VOL, VOH Ordering Information PART NUMBER CD54HC75F3A CD54HCT75F3A CD74HC75E CD74HC75M CD74HC75MT CD74HC75M96 CD74HC75NSR CD74HC75PW CD74HC75PWR CD74HCT75E CD74HCT75M CD74HCT75PWT TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -5……
