器件名称:
74AC11138N
功能描述:
3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
文件大小:
127.09KB 共8页
简 介:
74AC11138 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER SCAS042B – MAY 1988 – REVISED APRIL 1996 D D D D D D Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems Incorporates Three Enable Inputs to Simplify Cascading and/or Data Reception Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) 1-m Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline (D) and Thin Shrink Small-Outline (PW) Packages, and Standard Plastic 300-mil DIPs (N) D, N, OR PW PACKAGE (TOP VIEW) Y1 Y2 Y3 GND Y4 Y5 Y6 Y7 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 Y0 A B C VCC G1 G2A G2B description The 74AC11138 circuit is designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible. The conditions at the binary-select (A, B, C) inputs and the three enable (G1, G2A, G2B) inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-li……
