器件名称:
74AC11648
功能描述:
OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS
文件大小:
121.95KB 共9页
简 介:
74AC11648 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCAS114 – MARCH 1990 – REVISED APRIL 1993 Independent Registers for A and B Buses Multiplexed Real-Time and Stored Data Inverting Data Paths Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) 1-m Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs DW OR NT PACKAGE (TOP VIEW) description OE A1 A2 A3 A4 GND GND GND GND A5 A6 A7 A8 DIR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 CLKAB SAB B1 B2 B3 B4 VCC VCC B5 B6 B7 B8 CLKBA SBA The 74AC11648 consists of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the 74AC11648. Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the transceiver mode, data present at the high-impedance port may be stored in either register or in both. The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data.……
