器件名称:
74HC137
功能描述:
3-to-8 line decoder/demultiplexer with address latches; inverting
文件大小:
72.22KB 共8页
简 介:
INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT137 3-to-8 line decoder/demultiplexer with address latches; inverting Product specication File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specication 3-to-8 line decoder/demultiplexer with address latches; inverting FEATURES Combines 3-to-8 decoder with 3-bit latch Multiple input enable for easy expansion or independent controls Active LOW mutually exclusive outputs Output capability: standard ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT137 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. 74HC/HCT137 The 74HC/HCT137 are 3-to-8 line decoder/demultiplexers with latches at the three address inputs (An). The “137” essentially combines the 3-to-8 decoder function with a 3-bit storage latch. When the latch is enabled (LE = LOW), the “137” acts as a 3-to-8 active LOW decoder. When the latch enable (LE) goes from LOW-to-HIGH, the last data present at the inputs before this transition, is stored in the latches. Further address changes are ignored as long as LE remains HIGH. The output enable input (E1 and E2) controls the state of the outputs independent of the address inputs or ……
