器件名称:
74HC595
功能描述:
8-Bit Serial-Input/Serial or Parallel-Output Shift Register with Latched 3-State Outputs
文件大小:
248.98KB 共12页
简 介:
MC74HC595A 8-Bit Serial-Input/Serial or Parallel-Output Shift Register with Latched 3-State Outputs High–Performance Silicon–Gate CMOS The MC74HC595A consists of an 8–bit shift register and an 8–bit D–type latch with three–state parallel outputs. The shift register accepts serial data and provides a serial output. The shift register also provides parallel data to the 8–bit latch. The shift register and latch have independent clock inputs. This device also has an asynchronous reset for the shift register. The HC595A directly interfaces with the SPI serial data port on CMOS MPUs and MCUs. http://onsemi.com MARKING DIAGRAMS 16 16 1 PDIP–16 N SUFFIX CASE 648 MC74HC595AN AWLYYWW 1 16 Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 A High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 328 FETs or 82 Equivalent Gates Improvements over HC595 — Improved Propagation Delays — 50% Lower Quiescent Power — Improved Input Noise and Latchup Immunity LOGIC DIAGRAM SERIAL DATA INPUT A 14 15 1 2 QA QB PARALLEL DATA OUTPUTS 16 1 SO–16 D SUFFIX CASE 751B 1 HC595A AWLYWW 16 TSSOP–16 DT SUFFIX CASE 948F 1 A WL YY WW = Assembly Location = Wafer Lot = Year = Work Week HC 595A ALYW 16 1 PIN ASSIGNMENT QB QC QD QE QF QG QH GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC QA A OUTPUT ENABLE LATCH CLOCK ……
