器件名称:
74HCT573PW
功能描述:
OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
文件大小:
370.12KB 共11页
简 介:
SN54HCT573, SN74HCT573 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS176E – MARCH 1984 – REVISED JULY 2003 D D D D D D D D Operating Voltage Range of 4.5 V to 5.5 V High-Current 3-State Outputs Drive Bus Lines Directly or Up To 15 LSTTL Loads Low Power Consumption, 80-A Max ICC Typical tpd = 21 ns ±6-mA Output Drive at 5 V Low Input Current of 1 A Max Inputs Are TTL-Voltage Compatible Bus-Structured Pinout SN54HCT573 . . . J OR W PACKAGE SN74HCT573 . . . DB, DW, N, NS, OR PW PACKAGE (TOP VIEW) description/ordering information These octal transparent D-type latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The ’HCT573 devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. While the latch-enable (LE) input is high, the Q outputs respond to the data (D) inputs. When LE is low, the outputs are latched to retain the data that was set up at the D inputs. OE 1D 2D 3D 4D 5D 6D 7D 8D GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q LE SN54HCT573 . . . FK PACKAGE (TOP VIEW) 3D 4D 5D 6D 7D 4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 OE VCC 1Q 2Q 3Q 4Q 5Q 6Q TOP-SIDE MARKING 9 10 11 12 13 A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neithe……
