器件名称:
74LVQ125
功能描述:
Low Voltage Quad Buffer with 3-STATE Outputs
文件大小:
54.92KB 共5页
简 介:
74LVQ125 Low Voltage Quad Buffer with 3-STATE Outputs February 1992 Revised June 2001 74LVQ125 Low Voltage Quad Buffer with 3-STATE Outputs General Description The LVQ125 contains four independent non-inverting buffers with 3-STATE outputs. Features s Ideal for low power/low noise 3.3V applications s Guaranteed simultaneous switching noise level and dynamic threshold performance s Guaranteed pin-to-pin skew AC performance s Guaranteed incident wave switching into 75 Ordering Code: Order Number 74LVQ125SC 74LVQ125SJ Package Number M14A M14D Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol IEEE/IEC Connection Diagram Pin Descriptions Pin Names An , Bn On Description Inputs Outputs Truth Table Inputs An L L H H = HIGH Voltage Level L = LOW Voltage Level Z = HIGH Impedance X = Immaterial Output Bn L H X On L H Z 2001 Fairchild Semiconductor Corporation DS011349 www.fairchildsemi.com 74LVQ125 Absolute Maximum Ratings(Note 1) Supply Voltage (VCC ) DC Input Diode Current (IIK) VI = 0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = 0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current (ICC or IGND) Storage Temperature (TSTG) DC Latch-Up Source or Sink Current 0.5V to……
