器件名称:
EM44AM1684LBC-37F
功能描述:
256Mb (4M
文件大小:
408.87KB 共29页
简 介:
eorex Features JEDEC Standard VDD/VDDQ=1.8V ± 0.1V. All inputs and outputs are compatible with SSTL_18 interface. Fully differential clock inputs (CK,/CK) operation. 4 Banks Posted CAS Burst Length: 4 and 8. Programmable CAS Latency (CL): 3, 4 and 5. Programmable Additive Latency (AL): 0, 1, 2, 3 and 4. Write Latency (WL) =Read Latency (RL) -1. Read Latency (RL) = Programmable Additive Latency (AL) + CAS Latency (CL) Bi-directional Differential Data Strobe (DQS). Data inputs on DQS centers when write. Data outputs on DQS, /DQS edges when read. On chip DLL align DQ, DQS and /DQS transition with CK transition. DM mask write data-in at the both rising and falling edges of the data strobe. Sequential & Interleaved Burst type available. Off-Chip Driver (OCD) Impedance Adjustment On Die Termination (ODT) Auto Refresh and Self Refresh 8,192 Refresh Cycles / 64ms Average Refresh Period 7.8us at lower than Tcase 85° C, 3.9us at 85° C < Tcase ≦ 95° C RoHS Compliance Partial Array Self-Refresh (PASR) High Temperature Self-Refresh rate enable EM44AM1684LBC 256Mb (4M×4Bank×16) Double DATA RATE 2 SDRAM Description The EM44AM1684LBC is a high speed Double Date Rate 2 (DDR2) Synchronous DRAM fabricated with ultra high performance CMOS process containing 268,435,456 bits which organized as 4Mbits x 4 banks by 16 bits. This synchronous device achieves high speed double-data-rate transfer rates of up to 667 Mb/sec/pin (DDR2-667) for general applications. The chip is des……
