器件名称:
74VHCT374AMTR
功能描述:
OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT NON INVERTING
文件大小:
73.99KB 共10页
简 介:
74VHCT374A OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT NON INVERTING s s s s s s s s s s s HIGH SPEED: fMAX = 180 MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4 A (MAX.) at TA = 25 oC COMPATIBLE WITH TTL OUTPUTS: VIH = 2V (MIN), VIL = 0.8V (MAX) POWER DOWN PROTECTION ON INPUTS & OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 4.5V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 374 IMPROVED LATCH-UP IMMUNITY LOW NOISE VOLP = 0.9V (Max.) SOP TSSOP ORDER CODES PACKAGE SOP TSSOP T UBE 74VHCT374AM T& R 74VHCT374AMTR 74VHCT374ATTR DESCRIPTION The 74VHCT374A is an advanced high-speed CMOS OCTAL D-TYPE FLIP FLOP with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. This 8 bit D-Type flip-flop is controlled by a clock input (CK) and an output enable input (OE). On the positive transition of the clock, the Q outputs will be set to the logic state that were PIN CONNECTION AND IEC LOGIC SYMBOLS setup at the D inputs. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state. The output control does not affect the internal operation of flip flops; that is, the old data can be retained or the new data can be entered even while the outputs are off. Power down protection is provided on all inputs and ……
