器件名称: CD54HC237F3A
功能描述: High-Speed CMOS Logic, 3- to 8-Line Decoder/Demultiplexer with Address Latches
文件大小: 528.3KB 共19页
简 介:Data sheet acquired from Harris Semiconductor SCHS146F
CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237
High-Speed CMOS Logic, 3- to 8-Line Decoder/Demultiplexer with Address Latches
Both circuits have three binary select inputs (A0, A1 and A2) that can be latched by an active High Latch Enable (LE) signal to isolate the outputs from select-input changes. A “Low” LE makes the output transparent to the input and the circuit functions as a one-of-eight decoder. Two Output Enable inputs (OE1 and OE0) are provided to simplify cascading and to facilitate demultiplexing. The demultiplexing function is accomplished by using the A0, A1, A2 inputs to select the desired output and using one of the other Output Enable inputs as the data input while holding the other Output Enable input in its active state. In the CD74HC137 and CD74HCT137 the selected output is a “Low”; in the ’HC237 and CD74HCT237 the selected output is a “High”.
March 1998 - Revised October 2003
Features [ /Title (CD74 HC137 , CD74 HCT13 7, CD74 HC237 , CD74 HCT23 7) /Subject (High Speed
Select One of Eight Data Outputs - Active Low for CD74HC137 and CD74HCT137 - Active High for ’HC237 and CD74HCT237 l/O Port or Memory Selector Two Enable Inputs to Simplify Cascading Typical Propagation Delay of 13ns at VCC = 5V, 15pF, TA = 25oC (CD74HC237) Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads Wide Op……
