器件名称:
CPLL-018M-25-200.00
功能描述:
Programmable Clock Oscillator PLL Based Design 5X7 mm SMD, 3.3V, CMOS
文件大小:
116.94KB 共1页
简 介:
CPLL-018 Model 5X7 mm SMD, 3.3V, CMOS Frequency Range: Frequency Stability: Temperature Range: Operating: (Option M) (Option X) Storage: Input Voltage: Input Current: Output: Symmetry: Rise/Fall Time: Logic: Load: Jitter: Aging: ee Fr ad HS t e L Ro plian m Co 1.544MHz to 200MHz ±25ppm, ±50ppm, ±100ppm Programmable Clock Oscillator PLL Based Design 0°C to 70°C -20°C to 70°C -40°C to 85°C Designed to meet today's -55°C to 120°C requirements for economical 3.3V ± 0.3V 3.3V applications. Available 45mA Max on 16mm tape and reel in CMOS quantities of 1K. 40/60% Max @ 50% Vdd 10ns Max @ 20/% to 80% Vdd "0" = 80% Vdd Max "1" = 90% Vdd Min 15pF 150pS pk-pk Max <3ppm 1st/yr, <1ppm every year hereafter SUGGESTED PAD LAYOUT 0.055 Typ (1.40 Typ) #1 #2 #3 0.045 ±0.008 (1.14 ±0.20) 0.165 (4.19) 0.071 SQ (1.80) Dimensions inches (mm) All dimensions are Max unless otherwise specified. 0.295 Max (7.50) P/N Freq DC Denotes pad 1 0.204 Max (5.02) 0.075 Max (1.80) #4 0.200 ±0.005 (5.08 ±0.13) 0.200 (5.08) 0.01uF Bypass Capacitor Recommended RECOMMENDED REFLOW SOLDERING PROFILE TEMPERATURE 260°C 217°C 200°C 150°C Ramp-Up 3°C/Sec Max. Critical Temperature Zone Ramp-Down 6°C/Sec. Crystek Part Number Guide CPLL-018 X- 25 - 200.000 #1 #2 #3 #4 #5 #1 Crystek Clock PLL Osc. #2 Model #3 Temp. Range: Blank= 0/70°C, M= -20/70°C, X= -40/85°C #4 Stability: (see Table 1) #5 Frequency in MHz: 3 or 6 decimal places Stability Indicator Blank (std) 25 50 ± 100ppm ± 25ppm ± 50ppm Preheat 180 Secs.……
