器件名称:
M74HC51C1R
功能描述:
DUAL 2 WIDE 2 INPUT AND/OR INVERT GATE
文件大小:
234.95KB 共9页
简 介:
M54HC51 M74HC51 DUAL 2 WIDE 2 INPUT AND/OR INVERT GATE . . . . . . . . HIGH SPEED tPD = 10 ns (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 1 A (MAX.) AT TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE IOH = IOL = 4 mA (MIN.) BALANCED PROPAGATION DELAYS tPLH = tPHL WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V PIN AND FUNCTION COMPATIBLE WITH 54/74LS51 B1R (Plastic Package) F1R (Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) ORDER CODES : M54HC51F1R M74HC51M1R M74HC51B1R M74HC51C1R DESCRIPTION The M54/74HC51 is a high speed CMOS DUAL 2 WIDE-2 INPUT AND/OR INVERT GATE fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. It contains a 2WIDE 2-INPUT AND-OR-INVERT GATE and a 2WIDE 3-INPUT AND-OR-INVERT GATE. The internal circuit is composed of 3 stages (2INPUT) or 5 stages (3-INPUT) including buffered output, which gives high noise immunity and a stable output. All inputs are equipped with protection circuits against static discharge and transient excess voltage. INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN CONNECTIONS (top view) NC = No Internal Connection December 1992 1/9 M54/M74HC51 PIN DESCRIPTION PIN No 1, 12, 13, 9, 10, 11 2, 3, 4, 5 8, 6 7 14 SYMBOL 1A to 1F 2A to 2D 1Y, 2Y GND VCC NAME AND FUNCTION Data Inputs Data Inputs Data Outputs Ground (0V) Positive Supply Voltage IEC LOGIC……
