器件名称:
M74HCT139M1R
功能描述:
DUAL 2 TO 4 DECODER/DEMULTIPLEXER
文件大小:
267.05KB 共9页
简 介:
M74HCT139 DUAL 2 TO 4 DECODER/DEMULTIPLEXER s s s s s s HIGH SPEED: tPD = 17ns (TYP.) at VCC = 4.5V LOW POWER DISSIPATION: ICC = 4A(MAX.) at TA=25°C COMPATIBLE WITH TTL OUTPUTS : VIH = 2V (MIN.) VIL = 0.8V (MAX) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 139 DIP SOP TSSOP ORDER CODES PACKAGE DIP SOP TSSOP TUBE M74HCT139B1R M74HCT139M1R T&R M74HCT139RM13TR M74HCT139TTR DESCRIPTION The M74HCT139 is an high speed CMOS DUAL TWO LINE TO FOUR LINE DECODER/ DEMULTIPLEXER fabricated with silicon gate C2MOS technology. The active low enable input can be used for gating or as a data input for demultiplexing applications. While the enable input is held high, all four outputs are high independently of the other inputs. All inputs are equipped with protection circuits against static discharge and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS July 2001 1/9 M74HCT139 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1, 15 2, 3 4, 5, 6, 7 12, 11, 10, 9 14, 13 8 16 SYMBOL NAME AND FUNCTION 1G, 2G Enable Inputs 1A, 1B Address Inputs 1Y0 TO 1Y3 Outputs 2Y0 TO 2Y3 Outputs 2A, 2B GND VCC Address Inputs Ground (0V) Positive Supply Voltage TRUTH TABLE INPUTS ENABLE SELECT G H L L L L B X L L H H A X L H L H Y0 H L H H H Y1 H H L H H Y2 H H H L H Y3 H H H H L OUTPUTS SELECTED OUTPUT NONE Y0 Y1 Y2 Y3 LOGIC DIAGRAM This logic diagram has not be used to estimate p……
