器件名称:
MC74HC390ADR2
功能描述:
Dual 4-Stage Binary Ripple Counter with
文件大小:
204.04KB 共8页
简 介:
MC74HC390A Dual 4-Stage Binary Ripple Counter with ÷ 2 and ÷ 5 Sections High–Performance Silicon–Gate CMOS The MC74HC390A is identical in pinout to the LS390. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of two independent 4–bit counters, each composed of a divide–by–two and a divide–by–five section. The divide–by–two and divide–by–five counters have separate clock inputs, and can be cascaded to implement various combinations of ÷ 2 and/or ÷ 5 up to a ÷ 100 counter. Flip–flops internal to the counters are triggered by high–to–low transitions of the clock input. A separate, asynchronous reset is provided for each 4–bit counter. State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and should not be used as clocks or strobes except when gated with the Clock of the HC390A. Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 A High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No 7A Chip Complexity: 244 FETs or 61 Equivalent Gates LOGIC DIAGRAM ÷2 COUNTER 3, 13 http://onsemi.com MARKING DIAGRAMS 16 16 1 PDIP–16 N SUFFIX CASE 648 MC74HC390AN AWLYYWW 1 16 16 1 SO–16 D SUFFIX CASE 751B 1 HC390A AWLYWW 16 TSSOP–16 DT……
