器件名称:
M74HC131
功能描述:
3 TO 8 LINE DECODER/LATCH
文件大小:
262.65KB 共12页
简 介:
M54HC131 M74HC131 3 TO 8 LINE DECODER/LATCH . . . . . . . . HIGH SPEED tPD = 22 ns (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 4 A (MAX.) at TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE | IOH | = IOL = 4 mA (MIN.) BALANCED PROPAGATION DELAYS tPLH = tPHL WIDE OPERATING VOLTAGE RANGE VCC(OPR) = 2 V to 6 V PIN AND FUNCTION COMPATIBLE WITH 54/74LS131 B1R (Plastic Package) F1R (Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) ORDER CODES : M54HC131F1R M74HC131M1R M74HC131B1R M74HC131C1R PIN CONNECTIONS (top view) DESCRIPTION The M54/74HC131 is a high speed CMOS 3 TO 8 LINE DECODER/LATCH fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. This device is a DECODER/LATCH capable of selecting arbitrarily one of eight outputs by three binary inputs A, B, and C, in this case, the selected output is at logic ”low”. Also, when ENABLE input G1 is set low or ENABLE input G2 is set high, selection is inhibited regardless of other input signals and all the outputs are at high. All inputs are equipped with protection circuits against static discharge and transient excess voltage. October 1992 NC = No Internal Connection 1/12 M54/M74HC131 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1, 2, 3 4 5 6 9, 10, 11, 12, 13, 14, 15, 7 8 16 SYMBOL A, B, C CLK G2 G1 Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7 GND……
