器件名称:
M74HC137B1R
功能描述:
3 TO 8 LINE DECODER/LATCH INVERTING
文件大小:
256.38KB 共11页
简 介:
M54HC137 M74HC137 3 TO 8 LINE DECODER/LATCH (INVERTING) . . . . . . . . HIGH SPEED tPD = 11 ns (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 4 A (MAX.) AT TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE IOH = IOL = 4 mA (MIN.) BALANCED PROPAGATION DELAYS tPLH = tPHL WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V PIN AND FUNCTION COMPATIBLE WITH 54/74LS137 B1R (Plastic Package) F1R (Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) ORDER CODES : M54HC137F1R M74HC137M1R M74HC137B1R M74HC137C1R DESCRIPTION The M54/74HC137 is a high speed CMOS 3 TO 8LINE DECODER/LATCH (INVERTING) fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. This device is a 3 to 8line decoder withlatches on thethree address inputs. When GL goes from low tohigh, theaddress present at theselect inputs (A, B and C) is stored in the latches. As long as GL remains high no address changes will be recognized. Output enable pins G1 and G2, control the state of the outputs independently of the select or latch-enable inputs. All the outputs are high unless G1 is high and G2 is low. The HC137 is ideally suited for the implementation of glitch-free decoders in stored-address applications in bus oriented systems. All inputs are equipped withprotection circuits against staticdischarge and transient excess voltage. INPUT AND OUTPUT EQ……
