器件名称:
M74HC138M1R
功能描述:
3 TO 8 LINE DECODER INVERTING
文件大小:
242.32KB 共10页
简 介:
M54HC138 M74HC138 3 TO 8 LINE DECODER (INVERTING) . . . . . . . . HIGH SPEED tPD = 16 ns (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 4 A AT TA = 25 °C OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS BALANCED PROPAGATION DELAYS tPLH = tPHL SYMMETRICAL OUTPUT IMPEDANCE |IOH| = IOL HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V PIN AND FUNCTION COMPATIBLE WITH 54/74LS138 B1R (Plastic Package) F1R (Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) ORDER CODES : M54HC138F1R M74HC138M1R M74HC138B1R M74HC138C1R DESCRIPTION The M54/74HC138 is a high speed CMOS 3 TO 8 LINE DECODER fabricated in silicon gate C 2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. If the device is enabled, 3 binary select inputs (A, B and C) determine which one of the outputs will go low. If enable input G1 is held low or either G2A or G2B is held high, the decoding function is inhibited and all the 8 outputs go high. Three enable inputs are provided to ease cascade connection and application of address decoders for memory systems. All inputs are equipped with protection circuits against static discharge and transient excess voltage. INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN CONNECTIONS (top view) NC = No Internal Connection October 1992 1/10 M54/M74HC138 TRUTH TABLE INPUTS ENABLE G2B G2A X X X H H X L L L L L L L L L L L L L L L L X: Don’t Care G1 L X X H H H H H H H H C X X X……
