器件名称:
M74HC138RM13TR
功能描述:
3 TO 8 LINE DECODER (INVERTING)
文件大小:
283.1KB 共10页
简 介:
M74HC138 3 TO 8 LINE DECODER (INVERTING) s s s s s s s HIGH SPEED: tPD = 13ns (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC = 4A(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 138 DIP SOP TSSOP ORDER CODES PACKAGE DIP SOP TSSOP TUBE M74HC138B1R M74HC138M1R T&R M74HC138RM13TR M74HC138TTR DESCRIPTION The M74HC138 is an high speed CMOS 3 TO 8 LINE DECODER fabricated with silicon gate C2MOS technology. If the device is enabled, 3 binary select inputs (A, B, and C) determine which one of the outputs will go low. If enable input G1 is held low or either G2A or G2B is held high, the decoding function is inhibited and all the 8 outputs go high. Three enable inputs are provided to ease cascade connection and application of address decoders for memory systems. All inputs are equipped with protection circuits against static discharge and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS July 2001 1/10 M74HC138 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1, 2, 3 4, 5 6 9, 10, 11, 12, 13, 14, 15, 7 8 16 SYMBOL A, B, C G2A, G2B G1 Y0 to Y7 NAME AND FUNCTION Address Inputs Enable Inputs Enable Input Data Outputs GND VCC Ground (0V) Positive Supply Voltage TRUTH TABLE INPUTS OUTPUTS ENABLE G2B X X H L L L L L L L L G2A X H X L L L L L L ……
