器件名称:
M74HC237RM13TR
功能描述:
3 TO 8 LINE DECODER LATCH
文件大小:
181.57KB 共11页
简 介:
M74HC237 3 TO 8 LINE DECODER LATCH s s s s s s s HIGH SPEED: tPD = 16ns (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC = 4A(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 237 DIP SOP TSSOP ORDER CODES PACKAGE DIP SOP TSSOP TUBE M74HC237B1R M74HC237M1R T&R M74HC237RM13TR M74HC237TTR DESCRIPTION The M74HC237 is an high speed CMOS 3 TO 8 LINE DECODER fabricated with silicon gate C2MOS technology. When GL goes from low to high, the address present at the select inputs (A, B, C) is stored in the latches. As long as GL remains high no address changes will be recognized. Output enable controls, G1 and G2 control the state of the outputs independently of the select or latch-enable inputs. All of the outputs are low unless G1 is high and G2 is low. The M74HC237 is ideally suited for the implementation of glitch-free decoders in stored-address applications in bus oriented systems. All inputs are equipped with protection circuits against static discharge and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS July 2001 1/11 M74HC237 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1, 2, 3 4 5 6 15, 14, 13, 12, 11, 10, 9, 7 8 16 SYMBOL A, B, C GL G2 G1 Y0 to Y7 NAME AND FUNCTION Data Inputs Latch Enable Input Data Enable Input (Active LOW) Data……
