器件名称:
M74HC354C1R
功能描述:
8 CHANNEL MULTIPLEXER/REGISTER 3 STATE
文件大小:
264.37KB 共12页
简 介:
M54HC354 M74HC354 8 CHANNEL MULTIPLEXER/REGISTER (3 STATE) . . . . . . . . HIGH SPEED tPD = 24 ns (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 4 A (MAX.) AT TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 15 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE |IOH| = IOL = 6 mA (MIN.) BALANCED PROPAGATION DELAYS tPLH = tPHL WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V PIN AND FUNCTION COMPATIBLE WITH 54/74LS354 B1R (Plastic Package) F1R (Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) ORDER CODES : M54HC354F1R M74HC354M1R M74HC354B1R M74HC354C1R PIN CONNECTIONS (top view) DESCRIPTION The M54/74HC354 is a high speed CMOS 8-CHANNEL MULTIPLEXER/REGISTER (3-state) fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low consumption. This device contains an 8 channel digital multiplexer with an 8-bit input data register and a 3-bit address input register with 3-state outputs. The one of eight input data will be provided on the Y output pin (noninverted output) and W output pin (inverted output) determined by the address data. The information at the data inputs (D0 to D7) is stored in the 8-bit latch at the negative pulse on DC input. The information at the address inputs (S0 to S2) is stored in the 3-bit latch at the negative pulse on SC input. These outputs are disabled to be highimpedance when input G1 is held high, input G2 is held high or input G3 is held low. Th……
