器件名称:
M74HC373M1R
功能描述:
OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING
文件大小:
242.11KB 共11页
简 介:
M74HC373 OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING s s s s s s s HIGH SPEED: tPD = 12ns (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC = 4A(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 6mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 373 DIP SOP TSSOP ORDER CODES PACKAGE DIP SOP TSSOP TUBE M74HC373B1R M74HC373M1R T&R M74HC373RM13TR M74HC373TTR DESCRIPTION The M74HC373 is an high speed CMOS OCTAL LATCH WITH 3-STATE OUTPUTS fabricated with sub-micron silicon gate C2MOS technology. This 8-BIT D-Type latches is controlled by a latch enable input (LE) and output enable input (OE). While the LE input is held at a high level, the Q outputs will follow the data input. When the LE is taken low, the Q outputs will be latched at the logic level of D input data. While the OE input is at low level, the eight outputs will be in a normal logic state (high or low logic level) and when OE is in high level the outputs will be in a high impedance state. The 3-State output configuration and the wide choice of outline make bus organized system simple. All inputs are equipped with protection circuits against static discharge and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS July 2001 1/11 M74HC373 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1 2, 5, 6, 9, 12, 15, 16, 19 3, 4, 7, ……