器件名称: M74HC595C1R
功能描述: 8 BIT SHIFT REGISTER WITH OUTPUT LATCHES 3 STATE
文件大小: 282.9KB 共13页
简 介:M54HC595 M74HC595
8 BIT SHIFT REGISTER WITH OUTPUT LATCHES (3 STATE)
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HIGH SPEED fMAX = 55 MHz (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 4 A (MAX.) AT TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 15 LSTTL LOADS FOR QA TO QH 10 LSTTL LOADS FOR QH’ SYMMETRICAL OUTPUT IMPEDANCE |IOH| = IOL = 6 mA (MIN.) FOR QA TO QH |IOH| = IOL = 4 mA (MIN.) FOR QH’ BALANCED PROPAGATION DELAYS tPLH = tPHL WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V PIN AND FUNCTION COMPATIBLE WITH LSTTL 54/74LS595
B1R (Plastic Package)
F1R (Ceramic Package)
M1R (Micro Package)
C1R (Chip Carrier)
ORDER CODES : M54HC595F1R M74HC595M1R M74HC595B1R M74HC595C1R
PIN CONNECTIONS (top view)
DESCRIPTION The M54/74HC595 is a high speed CMOS 8-BIT SHIFT REGISTERS/OUTPUT LATCHES (32 STATE) fabricated in silicon C MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has 8 3-STATE outputs. Separate clocks are provided for both the shift register and the storage register. The shift register has a direct-overriding clear, serial input, and serial output (standard) pins for cascading. Both the shift register and storage register use positive-edge triggered clocks. If both clocks are connected together, the shift register state will always be one clock pulse ahead……
