器件名称:
MC74HC125ADR2
功能描述:
Quad 3-State Noninverting Buffers
文件大小:
171.14KB 共8页
简 介:
MC74HC125A, MC74HC126A Quad 3-State Noninverting Buffers High–Performance Silicon–Gate CMOS The MC74HC125A and MC74HC126A are identical in pinout to the LS125 and LS126. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC125A and HC126A noninverting buffers are designed to be used with 3–state memory address drivers, clock drivers, and other bus–oriented systems. The devices have four separate output enables that are active–low (HC125A) or active–high (HC126A). http://onsemi.com MARKING DIAGRAMS 14 PDIP–14 N SUFFIX CASE 646 MC74HC12xAN AWLYYWW 1 14 SOIC–14 D SUFFIX CASE 751A 1 14 TSSOP–14 DT SUFFIX CASE 948G HC 12xA ALYW HC12xA AWLYWW Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 A High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 72 FETs or 18 Equivalent Gates LOGIC DIAGRAM HC125A Active–Low Output Enables A1 OE1 A2 OE2 A3 OE3 A4 OE4 2 1 5 4 9 10 12 13 11 Y4 8 Y3 6 Y2 3 Y1 HC126A Active–High Output Enables A1 OE1 A2 OE2 A3 OE3 A4 OE4 2 1 5 4 9 10 12 13 11 Y4 8 Y3 6 Y2 3 Y1 1 A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week PIN ASSIGNMENT OE1 A1 Y1 OE2 A2 Y2 GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC OE4 A4 Y4 OE3 A3 Y3 PIN 14 = VCC PIN 7 = GND ORDERING INFORMATION Devi……
