器件名称:
74HCT161DB
功能描述:
Presettable synchronous 4-bit binary counter; asynchronous reset
文件大小:
83.61KB 共12页
简 介:
INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT161 Presettable synchronous 4-bit binary counter; asynchronous reset Product specication File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specication Presettable synchronous 4-bit binary counter; asynchronous reset FEATURES Synchronous counting and loading Two count enable inputs for n-bit cascading Positive-edge triggered clock Asynchronous reset Output capability: standard ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT161 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT161 are synchronous presettable binary counters which feature an internal look-ahead carry and can be used for high-speed counting. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset to a HIGH or LOW level. A LOW level at the parallel enable 74HC/HCT161 input (PE) disables the counting action and causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock (providing that the set-up and hold time requirements fo……
