器件名称:
CD54ACT1913A
功能描述:
Presettable Synchronous 4-Bit Binary Up/Down Counters
文件大小:
11.35KB 共1页
简 介:
S E M I C O N D U C T O R CD54AC191/3A CD54ACT191/3A Presettable Synchronous 4-Bit Binary Up/Down Counters Functional Diagram BINARY PRESET P0 15 ASYN. PARALLEL 11 LOAD ENABLE P1 1 P2 10 P3 9 3 2 CLOCK 14 6 7 UP/DOWN 5 Q2 Q3 Q0 Q1 BINARY OUTPUTS June 1997 COMPLETE DATA SHEET COMING SOON! Description The CD54AC191/3A and CD54ACT191/3A are asynchronously presettable binary up/down synchronous counters that utilize the Harris Advanced CMOS Logic technology. Presetting the counter to the number on preset data inputs (P0-P3) is accomplished by setting LOW the asynchronous parallel load input (PL). Counting occurs when PL is HIGH. Count Enable (CE) is LOW, and the Up/Down (U/D) input is either LOW for up-counting or HIGH for down-counting. The counter is incremented or decremented synchronously with the LOW-to-HIGH transition of the clock. When an overow or underow of the counter occurs, the Terminal Count (TC) output, which is LOW during counting, goes HIGH and remains HIGH for one clock cycle. This output can be used for look-ahead carry in high-speed cascading. The TC output also initiates the Ripple Clock (RC) output which, normally HIGH, goes LOW and remains LOW for the low-level portion of the clock pulse. These counters can be cascaded using the Ripple Count output. The CD54AC191/3A and CD54ACT191/3A are supplied in 16-lead dual-in-line ceramic packages (F sufx). 12 TERMINAL COUNT COUNT ENABLE 4 13 RIPPLE CLOCK ACT INPUT LOAD TABLE INPUT P0 - P3, PL CL, U/D, CE NOTE: 1……
