器件名称:
CD54HC147F3A
功能描述:
High-Speed CMOS Logic 10- to 4-Line Priority Encoder
文件大小:
492.32KB 共15页
简 介:
CD54HC147, CD74HC147, CD74HCT147 Data sheet acquired from Harris Semiconductor SCHS149F September 1997 - Revised November 2003 High-Speed CMOS Logic 10- to 4-Line Priority Encoder provide binary representation on the four active LOW inputs (Y0 to Y3). A priority is assigned to each input so that when two or more inputs are simultaneously active, the input with the highest priority is represented on the output, with input line l9 having the highest priority. These devices provide the 10-line to 4-line priority encoding function by use of the implied decimal “zero”. The “zero” is encoded when all nine data inputs are HIGH, forcing all four outputs HIGH. [ /Title (CD74 HC147 , CD74 HCT14 7) /Subject (High Speed CMOS Logic 10-to-4 Line Priority Encode r) /Autho r () /Keywords (High Speed CMOS Logic 10-to-4 Line Priority Encode r, High Speed CMOS Logic 10-to-4 Line Priority Features Buffered Inputs and Outputs Typical Propagation Delay: 13ns at VCC = 5V, CL = 15pF, TA = 25oC Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads Wide Operating Temperature Range . . . -55oC to 125oC Balanced Propagation Delay and Transition Times Signicant Power Reduction Compared to LSTTL Logic ICs HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VI……
