器件名称:
CD54HC194
功能描述:
High-Speed CMOS Logic 4-Bit Bidirectional Universal Shift Register
文件大小:
342.44KB 共15页
简 介:
CD54HC194, CD74HC194, CD74HCT194 Data sheet acquired from Harris Semiconductor SCHS164G September 1997 - Revised May 2006 High-Speed CMOS Logic 4-Bit Bidirectional Universal Shift Register Description The ’HC194 and CD74HCT194 are 4-bit shift registers with Asynchronous Master Reset (MR). In the parallel mode (S0 and S1 are high), data is loaded into the associated ip-op and appears at the output after the positive transition of the clock input (CP). During parallel loading serial data ow is inhibited. Shift left and shift right are accomplished synchronously on the positive clock edge with serial data entered at the shift left (DSL) serial input for the shift left mode, and at the shift right (DSR) serial input for the shift right mode. Clearing the register is accomplished by a Low applied to the Master Reset (MR) pin. Features [ /Title (CD74 HC194, CD74H CT194) /Subject (HighSpeed CMOS Logic 4-Bit Four Operating Modes - Shift Right, Shift Left, Hold and Reset Synchronous Parallel or Serial Operation Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25oC Asynchronous Master Reset Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads Wide Operating Temperature Range . . . -55oC to 125oC Balanced Propagation Delay and Transition Times Signicant Power Reduction Compared to LSTTL Logic ICs HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% o……
