器件名称:
CD54HC195
功能描述:
High-Speed CMOS Logic 4-Bit Parallel Access Register
文件大小:
632.02KB 共16页
简 介:
CD54HC195, CD74HC195 Data sheet acquired from Harris Semiconductor SCHS165E September 1997 - Revised October 2003 High-Speed CMOS Logic 4-Bit Parallel Access Register Description The device is useful in a wide variety of shifting, counting and storage applications. It performs serial, parallel, serial to parallel, or parallel to serial data transfers at very high speeds. The two modes of operation, shift right (Q0-Q1) and parallel load, are controlled by the state of the Parallel Enable (PE) input. Serial data enters the rst ip-op (Q0) via the J and K inputs when the PE input is high, and is shifted one bit in the direction Q0-Q1-Q2-Q3 following each Low to High clock transition. The J and K inputs provide the exibility of the JKtype input for special applications and by tying the two pins together, the simple D-type input for general applications. The device appears as four common-clocked D ip-ops when the PE input is Low. After the Low to High clock transition, data on the parallel inputs (D0-D3) is transferred to the respective Q0-Q3 outputs. Shift left operation (Q3-Q2) can be achieved by tying the Qn outputs to the Dn-1 inputs and holding the PE input low. All parallel and serial data transfers are synchronous, occurring after each Low to High clock transition. The ’HC195 series utilizes edge triggering; therefore, there is no restriction on the activity of the J, K, Pn and PE inputs for logic operations, other than set-up and hold time requirements. A Low on the async……
