器件名称:
CD54HC40105_07
功能描述:
High-Speed CMOS Logic 4-Bit x 16-Word FIFO Register
文件大小:
461.54KB 共21页
简 介:
CD54HC40105, CD74HC40105, CD54HCT40105, CD74HCT40105 Data sheet acquired from Harris Semiconductor SCHS222C February 1998 - Revised October 2003 High-Speed CMOS Logic 4-Bit x 16-Word FIFO Register Description The ’HC40105 and ’HCT40105 are high-speed silicon-gate CMOS devices that are compatible, except for “shift-out” circuitry, with the CD40105B. They are low-power rst-in-out (FIFO) “elastic” storage registers that can store 16 four-bit words. The 40105 is capable of handling input and output data at different shifting rates. This feature makes it particularly useful as a buffer between asynchronous systems. Each work position in the register is clocked by a control ipop, which stores a marker bit. A “1” signies that the position’s data is lled and a “0” denotes a vacancy in that position. The control ip-op detects the state of the preceding ip-op and communicates its own status to the succeeding ip-op. When a control ip-op is in the “0” state and sees a “1” in the preceeding ip-op, it generates a clock pulse that transfers data from the preceding four data latches into its own four data latches and resets the preceding ip-op to “0”. The rst and last control ip-ops have buffered outputs. Since all empty locations “bubble” automatically to the input end, and all valid data ripple through to the output end, the status of the rst control ip-op (DATA-IN READY) indicates if the FIFO is full, and the status of the last ip-op (DATAOUT READY) indicates if the FIFO contains data. ……
