器件名称: CD54HCT193F3A
功能描述: High-Speed CMOS Logic Presettable Synchronous 4-Bit Up/Down Counters
文件大小: 512.63KB 共20页
简 介:CD54/74HC192, CD54/74HC193, CD54/74HCT193
Data sheet acquired from Harris Semiconductor SCHS163F
September 1997 - Revised October 2003
High-Speed CMOS Logic Presettable Synchronous 4-Bit Up/Down Counters
Presetting the counter to the number on the preset data inputs (P0-P3) is accomplished by a LOW asynchronous parallel load input (PL). The counter is incremented on the low-to-high transition of the Clock-Up input (and a high level on the ClockDown input) and decremented on the low to high transition of the Clock-Down input (and a high level on the Clock-up input). A high level on the MR input overrides any other input to clear the counter to its zero state. The Terminal Count up (carry) goes low half a clock period before the zero count is reached and returns to a high level at the zero count. The Terminal Count Down (borrow) in the count down mode likewise goes low half a clock period before the maximum count (9 in the 192 and 15 in the 193) and returns to high at the maximum count. Cascading is effected by connecting the carry and borrow outputs of a less significant counter to the Clock-Up and Clock-Down inputs, respectively, of the next most significant counter. If a decade counter is preset to an illegal state or assumes an illegal state when power is applied, it will return to the normal sequence in one count as shown in state diagram.
Features [ /Title (CD74 HC192 , CD74 HC193 , CD74 HCT19 3) /Subject (High Speed CMOS Logic Preset Synchronous Counting and Asynchron……
