器件名称:
54ABT377J-QML
功能描述:
Octal D-Type Flip-Flop with Clock Enable
文件大小:
151.86KB 共8页
简 介:
54ABT377 Octal D-Type Flip-Flop with Clock Enable July 1998 54ABT377 Octal D-Type Flip-Flop with Clock Enable General Description The ’ABT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output. The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation. n n n n n n n n n n n Eight edge-triggered D flip-flops Buffered common clock See ’ABT273 for master reset version See ’ABT373 for transparent latch version See ’ABT374 for TRI-STATE version Output sink capability of 48 mA, source capability of 24 mA Guaranteed latchup protection High impedance glitch free bus loading during entire power up and power down cycle Non-destructive hot insertion capability Disable time less than enable time to avoid bus contention Standard Microcircuit Drawing (SMD) 5962-9314801 Features n Clock enable for address and data synchronization applications Ordering Code: Military 54ABT377J-QML 54ABT377W-QML 54ABT377E-QML Package Number J20A W20A E20A 20-Lead Ceramic Dual-In-Line 20-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier, Type C Package Description Connection Diagram Pin Assignment for DIP and Cerpack Pin Assignment……
